A conventional electrical signal is a voltage between an electrical conductor and another electrical conductor. The most common form of electrical signal is where one of the conductors is at ground potential and this form is usually referred to as unbalanced. There is also a common form of signal where neither conductor is at ground potential and each conductor carries a voltage relative to ground potential. This form of signal is usually referred to as balanced or differential.
Differential signals are the voltage difference between the conductors. The average potential of both conductors is usually referred to as the common-mode signal and that common-mode signal is equal on both conductors. Differential signals are the voltage difference between the conductors that represent the information carried by the signal and they vary around the common-mode voltage. When the differential signal on one conductor increases, the differential signal on the other conductor decreases by an equal amount, keeping the common-mode voltage constant.
A differential amplifier performs amplification of the differential signal value without any change in the common-mode value. Conventional use of a differential-in differential-out amplifier requires consideration of means to adjust the gain of the amplifier. Common practice uses amplifier in negative feedback configuration where the feedback through an external network determines the amplifier gain. Since this forms a closed loop signal path through the amplifier and the feedback network, it is usually referred to as closed loop gain or, more simply, gain. Closed loop gain represents how much an input signal is amplified at the output of the amplifier. The amplifier gain is commonly known as amp gain or amp open loop gain. Open loop gain is derived from amplifier gain and feedback factor. Open loop gain is measured by breaking the closed loop feedback circuit anywhere in the loop and measuring the gain at one of the broken end for an input signal applied to other end.
As each signal, differential and common-mode, passes through the differential amplifier circuit, special attention is required for treatment of the common-mode signal to minimize the effect on differential signal of the differential amplifier due to the common-mode value. This special attention usually takes the form of additional circuits and internal feedback dedicated to keep common-mode stable at the output. Usually the common-mode circuit consists of an extra gain stage and requires bandwidth large enough to suppress the even harmonic components; in general they consume a significant proportion of the power used by the whole circuit.
A differential amplifier can be either a differential-in differential-out amplifier or a differential-in single-ended-out differential amplifier. A differential-in differential-out amplifier circuit includes a signal path amplifier and a common mode feedback amplifier. A common mode feedback circuit is essential for differential-in differential-out amplifiers. A common mode feedback amplifier is a differential-in single-ended-out differential amplifier and is used to stabilize the output voltage in differential-in differential-out amplifiers. Throughout this application, terms “differential amplifier” and “differential-in differential-out amplifier” are used interchangeably. A more detailed explanation of a conventional differential-in and single-ended-out amplifier will now be discussed below with reference to FIG. 1.
FIGS. 1A and 1B illustrate an example conventional common mode feedback (CMFB) amplifier 100.
As illustrated in FIG. 1A, conventional CMFB amplifier 100 includes a differential amplifier 106, two singled-ended amplifiers 106a and 106b and two resistors 102a and 102b. Differential amplifier 106 is exclusively part of the CMFB path, whereas singled-ended amplifiers 106a and 106b and resistors 102a and 102b are actually part of the main differential amplifier (this will become clear later).
A voltage source 110 is arranged to generate an input signal 112 connected to the positive input of differential amplifier 106. Differential amplifier 106 is arranged to provide an output to single-ended amplifiers 106a and 106b. A first terminal of resistor 102a is arranged to receive output signal 114a from amplifier 106a and a first terminal of resistor 102b is arranged to receive output signal 114b from amplifier 106b. A second terminal of resistor 102a and a second terminal of resistor 102b are both joined to provide an input signal 116 to the negative input of differential amplifier 106.
Differential amplifier 106 has an open-loop gain of A106. The single-ended amplifiers 106a and 106b have open-loop gain of A106a and A106b, respectively. Nominally, A106a and A106b are equal. When CMFB amplifier 100 is configured as open-loop, i.e. resistors 102a and 102b are removed from the circuit, the magnitude of output signal 114a equals the voltage difference between the positive and negative inputs of differential amplifier 106 multiplied times the combined gain of differential amplifier 106 and single-ended amplifier 106a or A106×A106a. The voltage polarity of output signal 114a will be the inverse polarity of the voltage of the negative input to differential amplifier 106 and the same polarity of the voltage of the positive input to differential amplifier 106 subtracted from the voltage of the negative input to differential amplifier 106. Similarly the magnitude of output signal 114b equals the voltage difference between the positive and negative inputs of differential amplifier 106 multiplied by the combined gain of differential amplifier 106 and single-ended amplifier 106b or A106×A106b. The voltage polarity of output signal 114b will be the inverse polarity of the voltage of the negative input to differential amplifier 106 and the same polarity of the voltage of the positive input to differential amplifier 106 subtracted from the voltage of the negative input to differential amplifier 106. In close loop, that is when the second terminals of resistors 102a and 102b are connected to the negative input of differential amplifier 106, conventional CMFB amplifier 100 has gain of approximately one.
For the purpose of simplification, CMFB amplifier 100 shown in FIG. 1A can be represented by the equivalent circuit shown if FIG. 1B. In FIG. 1B, differential amplifier 106 and single-ended amplifiers 106a and 106b are combined into one equivalent differential-input single-ended output amplifier A106 and two resistors 102a and 102b are combined into one equivalent resistor 102. The equivalent CMFB 100 shown in FIG. 1A will be further used herein.
Conventional common mode feedback amplifier 100 allows the differential-in differential-out amplifier to have different common mode voltage at the input and the output and provides a stable common mode voltage level, which allows the output signal to use the full dynamic range of the output swing. Additionally, it suppresses any in-band even harmonic components from the signal path. Decoupling of the common mode component at the output signals of a differential amplifier enables the differential amplifier to realize its full dynamic range. Typically in a common mode feedback amplifier, the common mode value of output signal is fed back into the differential amplifier, which compares it with a stable DC reference voltage for removing the common mode component from the output signals of the differential amplifier. Ideally, the common mode signal should be a stable DC voltage.
A differential amplifier is connected in negative feedback configuration by connecting the output to the negative input through a feedback network. The voltage output of differential amplifier 106 gives a linear phase shift to its input with respect to frequency. In the situation where the output phase shift of differential amplifier 106 becomes 180° at a particular frequency, input and output signal would be in phase, thus becoming a positive feedback. A condition of input signal and output signal being in phase for differential amplifier 106 with a closed loop gain equal to one or greater than one, results in the circuit configuration of CMFB amplifier 100 becoming unstable. For differential amplifier 106, phase margin is defined as the phase shift due to differential amplifier 106, at a frequency where gain is 0 dB, subtracted from 180°. For example, if the phase shift of differential amplifier 106 were 135°, at a frequency where gain is 0 dB, then the phase margin for the circuit of CMFB amplifier 100 would be 45° (180°-135°=45°). Typically, a larger value of phase margin is desired, as a circuit with a small phase margin might be susceptible to instability.
Stability of differential amplifiers will be described in greater detail with reference to FIG. 2.
FIG. 2 includes a waveform 202 and a waveform 204, of conventional CMFB amplifier 100. The x-axis of each waveform is time, whereas the y-axis in each waveform is voltage. Waveform 202 represents a signal applied to the common-mode reference terminal of conventional CMFB amplifier 100 and waveform 204 represents typical oscillations superimposed on the common-mode signal, observed at the output of CMFB amplifier 100, due to common-mode instability or oscillation.
In the figure, waveform 202 indicates that the input signal to the common-mode reference terminal of conventional CMFB amplifier 100 is at 400 mV, as shown by a portion 206, before the CMFB amplifier 100 is turned on at a time 208. Waveform 204 indicates a portion 214, which may be in an unknown state, before the CMFB amplifier 100, is turned on.
To test the stability of the system, in this example, at time 208, a positive step signal is applied to the common-mode reference terminal of conventional CMFB amplifier 100 by increasing it to 600 mV from 400 mV. A stable common-mode feedback loop or a common-mode feedback loop with good phase margin will follow the stimulus. However, if common-mode feedback loop does not have enough phase margin or is unstable then it will start to oscillate with such a stimulus. This step change induces instability in the common-mode portion of CMFB amplifier 100. As such, as indicated by a portion 216 of waveform 204, the common-mode signal includes a high frequency signal having a high frequency and voltage varying between 200-700 mV. This high frequency oscillation continues throughout time period 210, indicating the instability of the loop. Next, a negative step stimulus is applied to ensure the correct loop operation across all conditions, as discussed below.
At a time 218, negative step signal is applied to the common-mode reference terminal of conventional CMFB amplifier 100 by decreasing its value to 400 mV from 600 mV. Even though the new 400 mV signal is applied throughout a time period 220, the input step change at time 218 induces instability in the common-mode portion of CMFB amplifier 100. As such, as indicated by a portion 222 of waveform 204, the common-mode signal is oscillating with a high frequency signal with amplitude varying between 0-500 mV. This high frequency signal continues throughout period 222.
The high frequency signal will continue as a result of the discontinuous and dramatic increase/decrease of an input pulse. Therefore, such an input pulse may be considered a type of stress test of the stability of a common-mode feedback amplifier. A greater increase/decrease of an input pulse in which a common-mode feedback amplifier can manage, without generating the high frequency signal such as waveform 204, translates into a more stable common-mode feedback amplifier. The stability of a common-mode feedback amplifier can increase with an increase in the phase margin.
FIG. 3 illustrates an example conventional differential-in differential-out amplifier 300.
Conventional differential-in differential-out amplifier 300 operates to amplify a differential between input signal Vi+ and input signal Vi− and provides an amplified and common mode adjusted differential output signal between output Vo+ and Vo−. The magnitude of the differential output signal is equal to a gain of differential-in differential-out amplifier 300 multiplied by the differential input signal. The common mode components of the differential output signal are adjusted in order to accommodate the different common mode components at the input and the output. The adjustment of the common mode components enables differential-in differential-out amplifier 300 to supply an output differential signal which is able to realize a wide dynamic range as provided by the source of power. The output differential signal overrides the common mode signal. An ideal common mode signal is a fixed DC voltage. If a common mode signal has such a large signal swing by itself then it reduces the available dynamic range for the differential signal and thus is not desirable.
As illustrated in the figure, differential-in differential-out amplifier 300 includes a differential amplifier 302, a feedback impedance portion 304, a current mirror portion 305 and a feedback circuit 306.
Feedback impedance portion 304 and feedback circuit 306 is a transistor level representation of the circuit of conventional CMFB amplifier 100 as illustrated in FIG. 1.
Differential amplifier 302 operates to amplify a differential between input signal Vi+ and Vi− and provide an amplified differential output signal between output signal Vo+ and Vo−. The differential output signal is equal to the gain of differential amplifier 302 multiplied by the differential input signal.
Feedback impedance portion 304 operates as a voltage divider in order to determine the common mode differential signal of Vo+ and Vo− and as denoted by a node 360.
Feedback circuit 306 operates to provide a feedback signal used for compensating or adjusting common mode components from Vo+ and Vo−. The common mode differential signal as denoted by node 360 is received by feedback circuit 306 in order to generate a signal for applying compensation to differential amplifier 302 for adjusting the common mode differential between Vi+ and Vi− from the output signals Vo+ and Vo−. Adjustment of the common mode differential enables differential-in differential-out amplifier 300 to realize the full dynamic range as provided by the differential between VDD and ground.
Differential amplifier 302 includes a PMOS tail current source 330, a positive input differential portion 314, a negative input differential portion 316, a positive output differential portion 318 and a negative output differential portion 320.
PMOS tail current source 330 operates to provide a source of current for positive input differential portion 314 and for negative input differential portion 316. Positive input differential portion 314 operates to receive and amplify input signal Vi+. Negative input differential portion 316 operates to receive and amplify Vi−. Positive output differential portion 318 and negative output differential portion 320 provide compensation to output signal Vo+ and Vo− for common mode differential as provided by input signal Vi+ and Vi−. Positive output differential portion 318 and negative output differential portion 320 also provide pole-frequency compensation in order to improve the phase margin of the entire amplifier.
PMOS tail current source 330 is connected between VDD and each of positive input differential portion 314 and negative input differential portion 316. Each of positive input differential portion 314 and negative input differential portion 316 are connected between PMOS tail current source 330 and ground. Each of positive output differential portion 318 and negative output differential portion 320 are connected between VDD and ground.
The source of PMOS tail current source 330 is connected to VDD, the gate of PMOS tail current source 330 is connected to a bias voltage 301 and the drain of PMOS tail current source 330 is connected to source of each of positive input differential portion 314 and negative input differential portion 316.
Positive input differential portion 314 includes a PMOS differential transistor 332 and an NMOS load transistor 334. The source of PMOS differential transistor 332 is connected to the drain of PMOS tail current source 330. The drain of PMOS differential transistor 332 is connected to the drain of NMOS load transistor 334. The gate of PMOS differential transistor 332 is arranged to receive positive input voltage Vi+. The source of NMOS load transistor 334 is connected to ground, whereas the gate of NMOS load transistor 334 is connected to negative input differential portion 316.
Negative input differential portion 316 includes a PMOS differential transistor 336 and an NMOS load transistor 338. The source of PMOS differential transistor 336 is connected to the drain of PMOS tail current source 330. The drain of PMOS differential transistor 336 is connected to the drain of NMOS load transistor 338. The gate of PMOS differential transistor 336 is arranged to receive negative input signal Vi−. The source of NMOS load transistor 338 is connected to ground, whereas the gate of NMOS load transistor 338 is connected to the gate of NMOS load transistor 334.
Positive output differential portion 318 includes a PMOS transistor 346, an NMOS transistor 348 and a compensation capacitor 350. The source of PMOS transistor 346 is connected to VDD. The drain of PMOS transistor 346 is connected to the drain of NMOS transistor 348. The gate of PMOS transistor 346 is connected to the gate of NMOS transistor 348. Compensation capacitor 350 is connected between the gate of PMOS transistor 346 (and the gate of PMOS transistor 346) and the drain of PMOS transistor 346 (and the drain of PMOS transistor 346). A node 352 provides a positive output signal Vo+ and is connected to feedback impedance portion 304.
Negative output differential portion 320 includes a PMOS transistor 340, an NMOS transistor 342 and a compensation capacitor 344. The source of PMOS transistor 340 is connected to VDD. The drain of PMOS transistor 340 is connected to the drain of NMOS transistor 342. The gate of PMOS transistor 340 is connected to the gate of NMOS transistor 342. Compensation capacitor 344 is connected between the gate of PMOS transistor 340 (and the gate of NMOS transistor 342) and the drain of PMOS transistor 340 (and the drain of NMOS transistor 342). A node 354 provides a negative output voltage Vo− and is connected to feedback impedance portion 304.
Feedback impedance portion 304 includes a resistor 356 and a resistor 358. One terminal of resistor 356 is connected to node 354, whereas the other terminal of resistor 356 is connected to node 360. One terminal of resistor 358 is connected to node 352, whereas the other terminal of resistor 358 is connected to node 360. Node 360 is additionally connected to feedback circuit 306.
Current mirror portion 305 includes a NMOS current mirror transistor 311 and a NMOS current mirror transistor 312. The gates of NMOS current mirror transistor 311 and NMOS current mirror transistor 312 are connected to feedback circuit 306. The sources of NMOS current mirror transistor 311 and NMOS current mirror transistor 312 are connected to ground. The drains of NMOS current mirror transistor 311 and NMOS current mirror transistor 312 are connected to differential amplifier 302.
Feedback circuit 306 is arranged to receive signal Vref as an input voltage. Feedback impedance portion 304 is arranged between feedback circuit 306 and differential amplifier 302. Referring to FIG. 1, feedback impedance portion 304 corresponds to resistor 102. The combination of feedback circuit 306 and differential amplifier 302 corresponds to differential amplifier 106. The signal Vref is desired output common mode voltage and is typically configured to a voltage value near the midpoint between VDD and ground.
Feedback circuit 306 includes a PMOS tail current source 308, a sensing leg 309 and a reference leg 310. The source of PMOS tail current source 308 is connected to VDD, the gate of PMOS tail current source 308 is connected to a bias voltage 301 and the drain of PMOS tail current source 308 is connected to each of sensing leg 309 and reference leg 310. Each of sensing leg 309 and reference leg 310 are connected between the drain of PMOS tail current source 308 and ground.
Sensing leg 309 includes a PMOS differential transistor 326 and an NMOS load transistor 328. The source of PMOS differential transistor 326 is connected to the drain of PMOS tail current source 308. The drain of PMOS differential transistor 326 is connected to the drain of NMOS load transistor 328. The gate of PMOS differential transistor 326 is connected to feedback impedance portion 304. There is an intrinsic capacitance from the gate of PMOS differential transistor 326 to the source of PMOS differential transistor 326. This intrinsic capacitance corresponds to intrinsic capacitance 104 of FIG. 1. The source of NMOS load transistor 328 is connected to ground, whereas the gate of NMOS load transistor 328 is connected to the drain of NMOS load transistor 328 as well as to the gate of NMOS current mirror transistor 311 and NMOS current mirror transistor 312. The sources of NMOS current mirror transistor 311 and NMOS current mirror transistor 312 are connected to ground. The drains of transistors 311 and 312 provide the feedback signal back to the amplifier 302. The drain of NMOS current mirror transistor 311 is connected to the drain of PMOS differential transistor 332, to the drain of NMOS load transistor 334 and the gate of NMOS transistor 342, to a terminal of compensation capacitor 344 and to the gate of PMOS transistor 340. The drain of NMOS current mirror transistor 312 is connected to the drain of PMOS differential transistor 336, to the drain of NMOS load transistor 338, to the gate of NMOS transistor 348, to a terminal of compensation capacitor 350 and to the gate of PMOS transistor 346.
Reference leg 310 includes a PMOS differential transistor 322 and an NMOS load transistor 324. The source of PMOS differential transistor 322 is connected to the drain of PMOS tail current source 308. The drain of PMOS differential transistor 322 is connected to the drain of NMOS load transistor 324. The gate of PMOS differential transistor 322 is arranged to receive signal Vref. The source of NMOS load transistor 324 is connected to ground, whereas the gate of NMOS load transistor 324 is connected to the drain of NMOS load transistor 324 to minimize the mismatch between the differential pair.
Current mirror portion 305 operates to mirror or replicate the current as realized through the drain of NMOS load transistor 328, i.e. if the current traversing through NMOS load transistor 328 increases, then the currents traversing through the drains of NMOS current mirror transistor 311 and NMOS current mirror transistor 312 also increase and vice-versa.
The common mode amplifier 306 of amplifier 300 controls the common mode value of the output signal Vo+ and Vo−. The common mode value of the differential output signal is also produced at node 360 of feedback impedance portion 304. The common mode differential is also received by the gate of PMOS differential transistor 326. A difference between the voltage applied to the gate of PMOS differential transistor 326 and signal Vref is fed back to the differential part 302 of the amplifier to form a negative feedback loop, which causes an increase or decrease in the amount of current traversing through the drain of PMOS differential transistor 326, such that the common mode voltage of the outputs Vo+ and Vo− comes closer to Vref.
A voltage at the gate of PMOS differential transistor 326 which is higher than Vref will cause the amount of current traversed through the drain of PMOS differential transistor 326 to decrease. A voltage at the gate of PMOS differential transistor which is lower than Vref will cause the amount of current traversed through the drain of PMOS differential transistor 326 to increase. A smaller current realized in NMOS load transistor 328 corresponds with a smaller current traversing through NMOS current mirror transistor 311 and NMOS current mirror transistor 312. A larger current realized in NMOS load transistor 328 corresponds with a larger current traversing through NMOS current mirror transistor 311 and NMOS current mirror transistor 312. A smaller amount of current traversing through NMOS current mirror transistor 311 and NMOS current mirror transistor 312 pushes the node 335 and node 347 to a higher voltage as current traversing through NMOS load transistor 334, NMOS load transistor 338, and PMOS tail current source 330 are constant.
The constant current traversing through PMOS tail current source 330 requires sum of the currents traversed through NMOS load transistor 334, NMOS load transistor 338, NMOS current mirror transistor 311 and NMOS current mirror transistor 312 to also be a constant. A smaller amount of current traversing through NMOS load transistor 311 and NMOS load transistor 312 results in the voltage applied to the gate of NMOS transistor 348 and NMOS transistor 342 to increase and vice-versa. A larger amount of current applied to the gate of NMOS transistor 348 and NMOS transistor 342 results in a larger amount of current traversing through the drains of NMOS transistor 348 and NMOS transistor 342 and vice-versa.
A larger amount of current traversing through the drains of NMOS transistor 348 and NMOS transistor 342 causes the voltages applied to output signals Vo+ and Vo− to be reduced and vice-versa. A reduction in the voltages applied to output signals Vo+ and Vo− is then reflected in the common mode differential as represented by node 360, which is also received by feedback circuit 306. This process is repeated until the voltage received at the gate of PMOS differential transistor 326 is the same voltage as applied to signal Vref. Once the voltage received at the gate of PMOS differential transistor 326 is the same as the voltage applied to signal Vref, the common mode of the differential signal as received by input signals Vi+ and Vi− is not produced at output signals Vo+ and Vo−. The common mode voltage of the output is placed to the desired voltage Vref. A more detailed explanation of the operation of differential-in differential-out amplifier 300 will now be described.
Presume that initially, Vref is 500 mV, whereas the voltage of the signal at the gate of PMOS differential transistor 326 is 450 mV. Because the voltage at the gate of PMOS differential transistor 326 is smaller than the voltage at the gate of PMOS differential transistor 322, sensing leg 309 will start to pull more current, via NMOS load transistor 328. The mirror legs 311 and 312 of NMOS load transistor 328 is arranged with constant current NMOS load transistor 334 of positive input differential portion 314, and with constant current NMOS load transistor 338 of negative input differential portion 316 to form a negative feedback loop. The total sum of current though NMOS transistors 334, 338, 311 and 312 is equal to the constant tail current of PMOS transistor 330.
To simplify the discussion, just consider one side of differential amplifier 302 (as both sides are equal). When the current is increasing through NMOS load transistor 328, then as a result of the properties of the current mirror arrangement, the current will increase through NMOS load transistor 311. When the current increases through NMOS load transistor 311, then the charge build-up at the drain of NMOS load transistor 338 will decrease—just imagine NMOS load transistor 338 sucking more charges down from its drain to its source. The drain of NMOS load transistor 338 is connected to the gate of NMOS transistor 348 and the gate of PMOS transistor 346. As such, when the amount of charge at the drain of NMOS load transistor 338 decreases, the amount of charge at the gate of NMOS transistor 348 and at the gate of PMOS transistor 346 further decreases. When the charge at the gate of NMOS transistor 348 and at the gate of PMOS transistor 346 additionally decreases, NMOS transistor 348 draws less current and PMOS transistor 346 provides more current, in turn voltage at the output Vo+ increases and moves closer to Vref. Accordingly, in such a case, the voltage at node 352 increases. This increase in voltage at node 352 increases the voltage at node 360, which then increases the voltage at the gate of PMOS differential transistor 326 and reduces the voltage difference between gates of PMOS differential transistor 326 and PMOS differential transistor 322.
In short, if the voltage Vo+ (and thus the voltage Vo−) is too low, the voltage at the gate of PMOS differential transistor 326 (sensing leg 309) will be lower than the voltage Vref at the gate of PMOS differential transistor 322 (reference leg 310). In response, a feedback arrangement will increase the voltage Vo+ (and thus the voltage Vo−), which will then increase the voltage at the gate of PMOS differential transistor 326 (sensing leg 309). But what happens if the voltage Vo+ (and thus the voltage Vo−) is increased too much, which will then increase the voltage at the gate of PMOS differential transistor 326 (sensing leg 309) too much? This will now be described.
Presume that initially, Vref is 500 mV, whereas the voltage at the gate of PMOS differential transistor 326 is 550 mV. Because the voltage at the gate of PMOS differential transistor 326 is more than the voltage at the gate of PMOS differential transistor 322, sensing leg 309 will start to pull less current, via NMOS load transistor 328. The mirror transistors NMOS 311 and 312 of NMOS load transistor 328 are arranged with NMOS load transistor 334 of positive input differential portion 314, and with NMOS load transistor 338 of negative input differential portion 316 to form the negative feedback loop. The total sum of current though NMOS transistors 334, 338, 311 and 312 is equal to the constant tail current of PMOS transistor 330.
To simplify the discussion, just consider one side of differential amplifier 302 (as both sides are equal). When the current is decreasing through NMOS load transistor 328, then as a result of the properties of the current mirror arrangement, the current will decrease through NMOS load transistor 311. When the current decreases through NMOS load transistor 311, then the charge build-up at the drain of NMOS load transistor 338 will increase—just imagine NMOS load transistor 338 sucking less charges down from its drain to its source, thus causing charges to build-up. The drain of NMOS load transistor 338 is connected to the gate of NMOS transistor 348 and the gate of PMOS transistor 346. As such, when the amount of charge at the drain of NMOS load transistor 311 increases, the amount of charge at the gate of NMOS transistor 348 and at the gate of PMOS transistor 346 additionally increases. When the charge at the gate of NMOS transistor 348 and at the gate of NMOS transistor 346 additionally increases, NMOS transistor 348 draws more current and PMOS transistor 346 provides less current to node 352. Accordingly, in such a case, the voltage at node 352 decreases. This decrease in voltage at node 352 decreases the voltage at node 360, which then decreases the voltage at the gate of PMOS differential transistor 326 and reduces the voltage difference between gate of PMOS differential transistors 326 and 322.
In short, if the voltage Vo+ (and thus the voltage Vo−) is too high, the voltage at the gate of PMOS differential transistor 326 (sensing leg 309) will be higher than the voltage Vref at the gate of PMOS differential transistor 322 (reference leg 310). In response, a feedback arrangement will decrease the voltage Vo+ (and thus the voltage Vo−), which will then decrease the voltage at the gate of PMOS differential transistor 326 (sensing leg 309).
The voltages at nodes 354 and 352 stabilizes around a predetermined value based on the voltage Vref as a result of the arrangement of differential amplifier 306, feedback impedance portion 304 and sensing leg 309.
Capacitors in semiconductor devices, for example compensation capacitors 344 and 350, typically require a significant amount of semiconductor geometric area. In general, differential amplifier 302 and feedback circuit 306 each require capacitors for operation. However, since capacitors in semiconductor devices require a significant amount of geometric area, the capacitors needed for differential amplifier 302 and feedback circuit 306 are shared as denoted by compensation capacitor 344 and compensation capacitor 350. Compensation capacitor 344 and compensation capacitor 350 have a dual purpose, as they serve the compensation capacitance needs for both differential amplifier 302 and feedback circuit 306. The capacitance value range needed for differential amplifier 302 to remain stable and the range needed for feedback circuit 306 to remain stable are different. In general, the capacitance values of compensation capacitor 344 and compensation capacitor 350 should fall within the range of capacitance values which are operable for both differential amplifier 302 and feedback circuit 306 to remain stable, i.e. realize sufficient phase margin in order to remain stable.
For stability of differential amplifier 306, it is desirable for the resistive portion of feedback impedance portion 304 to be a low resistance, i.e. the lower the resistance, higher the feedback pole is and more stable differential amplifier 306. However, a low resistive portion of feedback impedance portion 304 results in lower output impedance in-turn lower gain for the main signal path for differential amplifier 302, which is not desirable. Furthermore, a low resistive portion of feedback impedance portion 304 also starts to load the output stage and starts to direct a portion of the output signal power through feedback impedance portion 304 instead of to the load connected to output signals Vo+ and Vo−. Typically, it is desirable for the majority of the output signal power to be directed to the load being driven by output signals Vo+ and Vo−. As a result of the output load constraints, the resistive portion of feedback impedance portion 304 is typically selected to be at least a multiple of 10 times the load to be driven by output signals Vo+ and Vo−. However the higher resistive portion of feedback impedance portion 304 increases instability of common mode feedback amplifier 306 of the differential-in differential-out amplifier 300.
The capacitance constraints of compensation capacitors 344 and 350, i.e. shared constraints and stability constraints, combined with the resistive constraints for the resistive portion of feedback impedance portion 304, i.e. load and stability constraints, necessitate a geometric area size for compensation capacitors 344 and 350, which is relatively large. The relatively large geometric area typically required for compensation capacitors 344 and 350 results in increased costs for manufacturing conventional differential amplifier semiconductor devices.
In light of the above discussion, there are challenges in designing conventional common-mode, feedback amplifier 100. These challenges are drawn to the conflicting benefits and detriments of resistor 102 and parasitic capacitance 104.
Returning to FIG. 3, the output of conventional differential-in differential-out amplifier 300 is at node 352 and node 354. If the resistance value of feedback impedance portion 304 is relatively small, say for example, 100Ω, then it is beneficial for the operation of the common mode feedback. In this sense, it is better to keep the resistance value of feedback impedance portion 304, which corresponds to resistor 102 of FIG. 1, as a small value.
However, returning to FIG. 1, output signal 114 will take the path of least resistance. As such, in order to provide the majority of output signal 114 to the load, the resistance value of resistor 102 should be quite large, e.g., 100Ω or 10 times the resistance value of the load. The efficiency of conventional differential-in differential-out amplifier 300 may be measured in terms of the proportion of output signal 114 that is provided to the load. In other words, if more of output signal 114 is fed back through resistor 102, the less efficient the operation of conventional differential amplifier-in differential-out 300. In this sense, it is better to keep the resistance value of feedback impedance portion 304, which corresponds to resistor 102 of FIG. 1, as a very high value.
In light of the overall goals of maintaining beneficial operation of the common mode feedback and maintaining increased efficiency of conventional differential-in differential-out amplifier 300, it is difficult to choose an appropriate resistance value of feedback impedance portion 304.
To complicate matters, the capacitance value of parasitic capacitance 104 should be as small as possible. The product of the resistance value of resistor 102 and the capacitance value of parasitic capacitance 104, which is a pole in the feedback path, corresponds to a zero frequency in the feed-forward path. A zero in the feed-forward path boosts the gain and lags the phase, which in-turn worsens the phase margin of the common mode differential amplifier. Returning to FIG. 3, as discussed above feedback impedance portion 304 corresponds to resistor 102. Further, the intrinsic capacitance at the gate of PMOS differential transistor 326 corresponds to parasitic capacitance 104. To reduce the pole frequency, at least one of the resistance value of resistor 102 and the capacitance value of parasitic capacitance 104 must be reduced. In other words, to reduce the pole frequency, at least one of resistance value of feedback impedance portion 304 and the capacitance at the gate of PMOS differential transistor 326 must be reduced. To provide the maximum amount of output signal 114 to the load, the resistance value of feedback impedance portion 304 should not be reduced. Thus, to reduce the pole frequency, the capacitance at the gate of PMOS differential transistor 326 should be reduced. A smaller PMOS differential transistor means larger offset, which will reduce the swing in the output stage 346 and 340, in turn reducing the dynamic range.
Compensation capacitors are typically shared between a common-mode feedback path and a signal path of a differential-in differential-out amplifier. For example, returning to FIG. 3, compensation capacitors 344 and 350 are shared between the common-mode feedback path, e.g., positive output differential portion 318 and negative output differential portion 320, and the signal path, e.g., nodes 352 and 354.
To maximize the performance of a differential-in differential-out amplifier, generally a compensation capacitor is optimized based on the needs of differential-in differential-out amplifier. Since common mode feedback amplifier has one extra gain stage, optimization based only on the compensation capacitor is not sufficient. Based on the value of the compensation capacitor, the common mode feedback amplifier tends to oscillate and have a poor phase margin.
As discussed above using FIGS. 1-3, a conventional differential amplifier includes a signal path amplifier and a common-mode feedback path amplifier. Typically, the capacitance value of a compensation capacitor is set to maximize stability of a differential-in differential-out amplifier, when the closed loop gain is at its lowest value. For certain configurations, signal path of a differential amplifier may require reducing the compensation capacitor in order to improve its efficiency, resulting in an unstable common-mode feedback circuit. This may result in more power consumption because common-mode feedback circuit is a differential-in single-ended-out amplifier configured with a unity gain. The traditional implementation of a common-mode feedback amplifier, where a feedback resistor is connected between the output and input of the common-mode feedback circuit, may provide an unstable circuit. In order to improve stability of such a common-mode feedback circuit, a larger compensation capacitor may be required because of its high open loop gain, which may not be desirable by the signal path of a differential amplifier. Therefore, it's desirable to reduce the open loop gain of a common-mode feedback circuit in order to improve its stability without increasing the value of compensation capacitor.
What is needed is a stable differential amplifier that has a variable gain and that may be operated at low power.